Integrated circuit design requires adherence to a basic set of design ground rules. Additional recommended rules may apply when one wants to make design changes to improve production yield of a particular design. However, even when these rules are followed, some design changes can conflict. For example, adding redundant wiring vias improves the yield with regard to electrical opens, but can degrade the yield with regard to electrical shorts as a result of the expanded metal shapes associated with the additional vias.
Thus, determining the effects certain design changes will have on yield is an important factor in integrated circuit development. In most instances, it is impractical (if at all possible) to physically implement design changes and then ascertain how those changes impact the yield, especially given the costs associated with manufacturing today's high-density circuits. Take for instance the case of very-large-scale integration (VLSI) macros which contain hundreds of thousands to millions of elements. It would be impractical, both from a time and budgetary standpoint, to ‘mock up’ different designs in hopes of determining which design provides the best yield.
The most effective solution to this problem would be a process by which the yield of a given design could be predicted before any actual manufacturing takes place. With VLSI, however, the sheer number of elements present prevents conventional yield estimation techniques from operating in a time-effective manner. Thus, manufacturing capabilities become severely limited by the design process.
Therefore, techniques that permit yield prediction in real time for high-density integrated circuits, such as VLSI, would be desirable.